Optimizing a DSP Architecture for Wireless Baseband

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing.

The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.

The ConnX Baseband Engine is a configuration option package for Tensilca’s Xtensa LX customizable processor core. It implements a 3-way VLIW, 8-way SIMD architecture that can sustain 16 multiply-add operations per second and performance of a full radix-4 FFT butterfly per cycle. At 400 MHz, it provides almost 13GM per second of memory bandwidth and 1.6B complex FIR filter taps per cycle. It directly implements 8-way parallel division and 4-way parallel reciprocal square root operations.  And up to eight ConnX Baseband Engines can be used together for maximum performance.

The rich programming environment, including vectorization of scalar C applications, allows easy deployment of into complex applications.  In addition, the Xtensa processor family, including the ConnX Baseband Engine, supports easy integration of multiple cores with high-bandwidth memory and direct port interconnect among each tightly-coupled cluster of cores.  The ConnX Baseband Engine is specifically designed for digital television, cellular basestation, femto-cell and other software-agile radio applications and is also being used to provide full programmability for  multi-standard broadcast receivers.

The Challenge of Emerging Wireless Standards

Emerging wireless standards, such as 3GPP (3rd Generation Partnership Project), LTE (Long Term Evolution) and LTE Advanced, present significant challenges for baseband processing. The wireless subsystem must be efficient in both energy usage and silicon area requirements. The subsystem must implement all modes of one or more baseband communications standard. Also, it may be expected to provide enough programmability to support unanticipated enhancements, additional standards, and bug fixes.

The energy and area demands are particularly intense for the handset. The requirement for ample flexibility is particularly intense for femto-cell and base-station implementations. All form factors share a common challenge in rapid and complete development of the wide range of features required in modern wireless protocols.

Existing DSP architectures cannot meet these demands, and vendors are scrambling to develop new, more efficient and powerful architectures. This paper describes a new digital signal architecture tuned for the demands of highly programmable baseband processing at 100 Mbps delivered data rates.

Tensilica’s ConnX Baseband Engine architecture includes an optimized instruction set and memory system targeting high throughput and low power for emerging baseband PHY standards, especially those using Orthogonal Frequency Division Multiplexing (IFDM) modulation and Multiple Input Multiple Output (MIMO) transmission. Easy programmability, including automatic vectorization for ANSI C programs and optimized instructions for fast complex FFT, FIR and matrix operations make the new architecture particularly suitable for cost-oriented base-stations, femto-cells, digital media broadcast receivers and software-defined-radio handsets.

The Challenge of Baseband Processing

The drive for higher data rates in wireless systems drives two basic trends in wireless channel design. First, wider frequency bands are allocated to cellular communications, significantly increasing data rates and computation requirements. Second, much more aggressive modulation and encoding schemes are used to squeeze maximum spectral efficiency out of that bandwidth. More aggressive modulation, such as 64-QAM, more complex time and frequency allocations, such as OFDM, and exploitation of antenna diversity, such as MIMO, dramatically add to the computation requirements per bit of nominal bandwidth.

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